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preliminary: the specification of this device are subject to change without notice. please contact your nearest hitachi? sales dept. regarding specification. HM628128DI series 1 m sram (128-kword 8-bit) ade-203-999a (z) preliminary rev. 0.1 jul. 8, 1999 description the hitachi HM628128DI series is 1-mbit static ram organized 131,072-kword 8-bit. HM628128DI series has realized higher density, higher performance and low power consumption by employing hi-cmos process technology. the HM628128DI series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it has package variations of standard 32-pin plastic dip, standard 32-pin plastic sop. features single 5 v supply: 5 v 10% access time: 70 ns (max) power dissipation ? active: 30 mw/mhz (typ) ? standby: 10 m w (typ) completely static memory. ? no clock or timing strobe required equal access and cycle times common data input and output ? three state output directly ttl compatible all inputs battery backup operation ? 2 chip selection for battery backup temperature range: ?0 to +85 c
HM628128DI series 2 ordering information type no. access time package hm628128dlpi-7 70 ns 600-mil 32-pin plastic dip (dp-32) hm628128dlfpi-7 70 ns 525-mil 32-pin plastic sop (fp-32d)
HM628128DI series 3 pin arrangement 32-pin dip/sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc a15 cs2 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 (top view) pin description pin name function a0 to a16 address input i/o0 to i/o7 data input/output cs1 chip select 1 cs2 chip select 2 we write enable oe output enable v cc power supply v ss ground nc no connection
HM628128DI series 4 block diagram i/o0 i/o7 we oe a14 a16 a15 a8 a11 v cc v ss row decoder memory matrix 512 x 2,048 column i/o column decoder input data control timing pulse generator read/write control a9 a12 a7 a6 a5 a4 a3 a2 a1 a0 a10 a13 msb lsb msb lsb cs1 cs2
HM628128DI series 5 operation table cs1 cs2 we oe i/o operation h high-z standby l high-z standby l h h l dout read l h l h din write l h l l din write l h h h high-z output disable note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?.5 to +7.0 v terminal voltage on any pin relative to v ss v t ?.5* 1 to v cc + 0.3* 2 v power dissipation p t 1.0 w storage temperature range tstg ?5 to +125 c storage temperature range under bias tbias ?0 to +85 c notes: 1. v t min: ?.5 v for pulse half-width 30 ns 2. maximum voltage is +7.0 v dc operating conditions parameter symbol min typ max unit note supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high voltage v ih 2.4 v cc + 0.3 v input low voltage v il ?.3 0.6 v 1 ambient temperature range ta ?0 85 c note: 1. v il min: ?.5 v for pulse half-width 30 ns
HM628128DI series 6 dc characteristics parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs1 = v ih or cs2 = v il or oe = v ih or we = v il , v i/o = v ss to v cc operating current i cc 15ma cs1 = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma average operating current i cc1 60 ma min cycle, duty = 100% i i/o = 0 ma, cs1 = v il , cs2 = v ih , others = v ih /v il i cc2 6 20 ma cycle time = 1 m s, duty = 100%, i i/o = 0 ma, cs1 0.2 v, cs2 3 v cc ?0.2 v, v ih 3 v cc ?0.2 v, v il 0.2 v standby current i sb 2 ma (1) cs1 = v ih , cs2 = v ih , or (2) cs2 = v il i sb1 * 2 2 100 m a 0 v vin (1) 0 v cs2 0.2 v or (2) cs1 3 v cc ?0.2 v, cs2 3 v cc ?0.2 v output high voltage v oh 2.4 v i oh = ? ma output low voltage v ol 0.4 v i ol = 2.1 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and specified loading, and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = +25 c, f = 1 mhz) parameter symbol typ max unit test conditions note input capacitance cin 8 pf vin = 0 v 1 input/output capacitance c i/o ?0pfv i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested.
HM628128DI series 7 ac characteristics (ta = ?0 to +85 c, v cc = 5.0 v 10%, unless otherwise noted.) test conditions input pulse levels: v il = 0.6 v, v ih = 2.4 v input rise and fall time: 5 ns input timing reference levels: 1.5 v output timing reference level: 1.5 v output load:1 ttl gate+ cl (100 pf) (including scope and jig) read cycle HM628128DI -7 parameter symbol min max unit notes read cycle time t rc 70 ns address access time t aa ?0ns chip select access time t acs1 ?0ns t acs2 ?0ns output enable to output valid t oe ?5ns output hold from address change t oh 10 ns chip selection to output in low-z t clz1 10 ns 2, 3 t clz2 10 ns 2, 3 output enable to output in low-z t olz 5 ns 2, 3 chip deselection to output in high-z t chz1 0 25 ns 1, 2, 3 t chz2 0 25 ns 1, 2, 3 output disable to output in high-z t ohz 0 25 ns 1, 2, 3
HM628128DI series 8 write cycle HM628128DI -7 parameter symbol min max unit notes write cycle time t wc 70 ns address valid to end of write t aw 60 ns chip selection to end of write t cw 60 ns 5 write pulse width t wp 50 ns 4, 13 address setup time t as 0 ns 6 write recovery time t wr 0 ns 7 data to write time overlap t dw 30 ns data hold from write time t dh 0ns output active from output in high-z t ow 5 ns 2 output disable to output in high-z t ohz 0 25 ns 1, 2, 8 we to output in high-z t whz 0 25 ns 1, 2, 8 notes: 1. t chz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit?onditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temperature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the overlap (t wp ) of a low cs1 , a high cs2, and a low we . a write begins at the latest transition among cs1 going low, cs2 going high, and we going low. a write ends at the earliest transition among cs1 going high, cs2 going low, and we going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from cs1 going low or cs2 going high to the end of write. 6. t as is measured from the address valid to the beginning of write. 7. t wr is measured from the earlier of we or cs1 going high or cs2 going low to the end of write cycle. 8. during this period, i/o pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. if the cs1 goes low or cs2 going high simultaneously with we going low or after we going low, the output remain in a high impedance state. 10. dout is the same phase of the write data of this write cycle. 11. dout is the read data of next address. 12. if cs1 is low and cs2 high during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp 3 t dw min + t whz max
HM628128DI series 9 timing waveforms read cycle ( we = v ih ) t aa t acs1 t rc t clz1 t oe t olz t chz2 t ohz valid data address cs1 oe dout t oh cs2 valid address t acs2 t clz2 high impedance t chz1
HM628128DI series 10 write cycle (1) ( oe clock) address cs1 we dout din t wc t cw t wr t wp t ohz t dw t dh *9 valid address t aw cs2 t as high impedance valid data oe
HM628128DI series 11 write cycle (2) ( oe = v il ) address cs1 we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *12 *10 *11 *9 valid address valid data cs2 high impedance
HM628128DI series 12 low v cc data retention characteristics (ta = ?0 to +85 c) parameter symbol min typ * 3 max unit test conditions * 2 v cc for data retention v dr 2.0 v vin 3 0v (1) 0 v cs2 0.2 v or (2) cs2 3 v cc ?0.2 v cs1 3 v cc ?0.2 v data retention current i ccdr * 1 1.0 50 m av cc = 3.0 v, vin 3 0 v (1) 0 v cs2 0.2 v or (2) cs2 3 v cc ?0.2 v, cs1 3 v cc ?0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc * 4 ns notes: 1. this characteristic is guaranteed only for l-version, 30 m a max. at ta = ?0 to +40 c. 2. cs2 controls address buffer, we buffer, cs1 buffer, oe buffer, and din buffer. if cs2 controls data retention mode, vin levels (address, we , oe , cs1 , i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v. the other input levels (address, we , oe , i/o) can be in the high impedance state. 3. typical values are at v cc = 3.0 v, ta = +25 c and specified loading, and not guaranteed. 4. t rc = read cycle time. low v cc data retention timing waveform (1) ( cs1 controlled) v cc 4.5 v 2.4 v 0 v cs1 t cdr t r cs1 3 v cc ?0.2 v v dr data retention mode
HM628128DI series 13 low v cc data retention timing waveform (2) (cs2 controlled) v cc 4.5 v 0 v cs2 t r v dr data retention mode 0.6 v t cdr 0 v cs2 0.2 v
HM628128DI series 14 package dimensions hm628128dlpi series (dp-32) hitachi code jedec eiaj weight (reference value) dp-32 conforms 5.1 g unit: mm 0.51 min 2.54 min 5.08 max 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 41.90 42.50 max 13.4 13.7 max 15.24 32 17 1 16 2.30 max 1.20
HM628128DI series 15 hm628128dlfpi series (fp-32d) hitachi code jedec eiaj weight (reference value) fp-32d conforms 1.3 g unit: mm *dimension including the plating thickness base material dimension 0.15 m *0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max *0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04
HM628128DI series 16 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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